A. Field of the Invention
The present invention relates to demodulators, and, more particularly to demodulators which are suitable for demodulating a modulated high frequency carrier signal. Specifically, the invention relates to a digital demodulator for demodulating an on-off keyed high frequency carrier in which the presence of carrier indicates a logic "1" and the absence of carrier indicates a logic "0". While the digital demodulator of the present invention is of general application it has particular application to and will be described in connection with a large scale integrated circuit, referred to as a digital IC, which is used as the basic building block in a communication and control network in which a large number of remotely located controllable devices, such as circuit breakers, motor controllers, lighting control systems, and the like, may be controlled from a central or master controller using the conventional AC power lines as the common data line.
B. Description of the Prior Art
When a conventional power line is used as the common data line in a communication and control network considerably difficulty is experienced in transmitting messags over the power line due to the relatively high noise level thereon. Various communication and control systems have been heretofore proposed for controlling a group of remotely located devices from a central controller over a conventional power line. One such communication and control system is shown in Eichelberger et al U.S. Pat. No. 4,091,361. In this patent digital addresses and function codes are transmitted by frequency-shift keying (FSK) modulation which is superimposed on the AC signal present on the power line. A phase-locked loop circuit is employed to detect the frequency-shift keyed signal. Noise immunity is said to be achieved by delaying performance of the function until the correct address portion of the transmitted message has been received at least two times out of three. However, such a redundant signalling arrangement takes considerably more time for each transmitted message and hence greatly reduces the throughput of such a communication and control system. Also, the system disclosed in U.S. Pat. No. 4,091,361 operates at the very low bawd rate of 120 bits per second.
In Miller et al U.S. Pat. Nos. 4,367,414 and 4,396,844 a communication and control system is disclosed in which a message transmitted over the network includes a preamble portion of a minimum of four bits. These preamble bits comprise 50% square waves which are utilized by the transceiver decoders to permit a phase lock loop circuit in each transceiver to lock onto the received preamble bits. The use of a minimum of four bits to provide phase loop lockon reducing the overall throughput of such a system. Also, in order to capture the preamble bits it is necessary to provide the phase lock loop circuit initially with a relatively wide bandwidth of about SKHz and the narrow down the bandwidth after the phase lock loop circuit has locked onto the preamble bits. Such an arrangement requires additional circuitry to accomplish the necessary change in bandwidth. Also, the relatively wide bandwidth necessary to capture the preamble bits also lets in more noise so that the security and reliability of the system is reduced in noisy environments such as a power line.